The DMSO HLA Example

Introduction

The High Level Architecture (HLA) is developed by the Department of Defense (DoD) for modeling and simulation (M&S). The purpose of this architecture is to facilitate interoperability among simulations and promote reuse of simulations and their components. Rapide is a concurrent event-based simulation language for defining and simulating the behavior of system architectures. Rapide is intended for modelling the architectures of concurrent and distributed systems, both hardware and software. The aim of this example is to model HLA in Rapide.

There is also a slide show that introduces the demo. Click here for an overview figure of how Rapide is used in exploring the HLA definition (or here for the PostScript version).

Publications

Applying Event-Based Modelling to the ADS High Level Architecture Development Process , David Luckham, Francois Guimbretiere, Hai-Geng Wang and Yung-Hsiang Lu. 14 page unpublished paper.
Discussion of the demonstration of Rapide in modeling the HLA interface definition.
HLA Demonstration Sources , Yung-Hsiang Lu and Francois Guimbretiere. 30 page unpublished paper.
A brief description and Rapide sources for the Level 2 HLA simulation.

Representations

Three different GIF representations of the architecture are available, corresponding to three different levels of detail:

The interface only. (Click here for the PostScript version)
The interface with minimum internal structure in RTI (run time infrastructure) (Click here for the PostScript version)
A proposed implementation of the RTI. (Click here for the PostScript version)

A PostScript simulation output poset is also available.

For More Information

See the pages for DMSO and the DMSO HLA.

Back to the Rapide home page.

mann@pavg.stanford.edu